26 citations · 33 across the 4 of their papers we have counts for
5 papers · 1 filter
Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC
Nick Brown, Maurice Jamieson
Whilst RISC-V has grown phenomenally quickly in embedded computing, it is yet to gain significant traction in High Performance Computing (HPC). However, as we move further into the…
A shared compilation stack for distributed-memory parallelism in stencil DSLs
George Bisbas, Anton Lydike, Emilien Bauer +8
Domain Specific Languages (DSLs) increase programmer productivity and provide high performance. Their targeted abstractions allow scientists to express problems at a high level, pr…
Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA
Gabriel Rodriguez-Canal, Nick Brown, Maurice Jamieson +3
The challenges associated with effectively programming FPGAs have been a major blocker in popularising reconfigurable architectures for HPC workloads. However new compiler technolo…
Fortran performance optimisation and auto-parallelisation by leveraging MLIR-based domain specific abstractions in Flang
Nick Brown, Maurice Jamieson, Anton Lydike +2
MLIR has become popular since it was open sourced in 2019. A sub-project of LLVM, the flexibility provided by MLIR to represent Intermediate Representations (IR) as dialects at dif…
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU
Nick Brown, Maurice Jamieson, Joseph Lee +1
The Sophon SG2042 is the world's first commodity 64-core RISC-V CPU for high performance workloads and an important question is whether the SG2042 has the potential to encourage th…