3 papers
cs.AR2026
Coverage-Driven RTL Assertion Generation with Formal Exploration and Neuro-Symbolic Refinement
Zhiyuan Yan, Ziyue Zheng, Hongce Zhang
Hardware functional verification relies on high-quality assertions to expose design bugs and establish confidence in Register Transfer Level (RTL) designs. Yet existing assertion m…
cs.AR2026
NeuroAbs: A Neuro-Symbolic RTL Abstraction Framework for Property Checking Acceleration
Zhiyuan Yan, Xiaofeng Zhou, Ziyue Zheng +5
Formal verification is a crucial technique for ensuring the functional correctness of hardware designs. In the context of property checking, a key challenge is how to efficiently p…
cs.AR2026
Forbench: Symbolic Simulation Helps Make Your Testbench More Formal
Ziyi Yang, Wenbin Che, Ziyue Zheng +2
Simulation remains the dominant approach in pre-silicon verification due to its ease of deployment and intuitive workflow. However, as simulation only explores a limited subset of…