2 papers
cs.AR2026
PANEM: A Heuristic Latency Model
Lucas Crowthers, Mahesh Madhav
Accurate pre-silicon memory modeling is essential for achieving meaningful representation of workloads on cloud-class many-core processors. Existing options force a poor tradeoff b…
cs.AR2026
Performance Verification of the AmpereOne CPU Core
Doa'a Al-Otoom, Nicholas Kelly, Aaron Lindsay +16
As process technology scaling slows, microarchitectural innovation has become the primary driver of performance gains, making pre-silicon Performance Verification (PV) more critica…