2 papers
cs.AR2026
PACT: Post-route Agentic Checkpoint Tuning for FPGA Timing Closure
Huan Lin, Kunlong Li, Lingli Wang +1
Late-stage FPGA timing closure often starts from an implemented design whose remaining violations are visible in timing reports. Engineering change order (ECO) optimization is a st…
cs.AR2026
StateTune: Transforming LLM-Assisted EDA Flow Tuning into a Stateful, Closed-Loop Process
Kunlong Li, Shangshang Yao, Su Zheng +1
EDA flow parameter tuning is critical for quality-of-results~(QoR), yet the parameter space is large, tightly coupled, and full evaluations are prohibitively expensive. Prior LLM-a…