2 papers
cs.SE2026
AgentDV: Closed-Loop Agentic AI for Hardware Design Verification
Navya Goli, Junzhe Liu, Zhenge Jia +1
Register-transfer level (RTL) verification consumes a major part of modern system-on-chip (SoC) development effort. Yet, recent LLM-based verification-code generation often fails t…
cs.SE2025
SysVCoder: An LLM-Driven Framework for Systematic Generation of System-Level Design
Jian Zuo, Junzhe Liu, Xianyong Wang +6
Recent advances in large language models (LLMs) have demonstrated strong potential in generating hardware designs using hardware description languages (HDLs) such as Verilog. Howev…