8 papers
FusionCell: Cross-Attentive Fusion of Layout Geometry and Netlist Topology for Standard-Cell Performance Prediction
Haoyi Zhang, Kairong Guo, Bojie Zhang +2
Standard cells form the building blocks of digital circuits, so their delay and power critically influence chip-level performance; yet characterization still relies on slow simulat…
LaMoSys3.5D: Enabling 3.5D-IC-Based Large Language Model Inference Serving Systems via Hardware/Software Co-Design
Qipan Wang, Zhe Zhang, Shuangchen Li +5
The success of large language models LLMs amplifies the need for highthroughput energyefficient inference at scale. 3DDRAMbased accelerators provide high memory bandwidth and there…
ATMPlace: Analytical Thermo-Mechanical-Aware Placement Framework for 2.5D-IC
Qipan Wang, Tianxiang Zhu, Tianyu Jia +3
Rising demand in AI and automotive applications is accelerating 2.5D IC adoption, with multiple chiplets tightly placed to enable high-speed interconnects and heterogeneous integra…
HeteroSTA: A CPU-GPU Heterogeneous Static Timing Analysis Engine with Holistic Industrial Design Support
Zizheng Guo, Haichuan Liu, Xizhe Shi +5
We introduce in this paper, HeteroSTA, the first CPU-GPU heterogeneous timing analysis engine that efficiently supports: (1) a set of delay calculation models providing versatile a…
SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support
Haikang Diao, Haoyi Zhang, Jiahao Song +5
Digital computing-in-memory (DCIM) has been a popular solution for addressing the memory wall problem in recent years. However, the DCIM design still heavily relies on manual effor…
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis
Xun Jiang, Haoran Lu, Yuxuan Zhao +8
As the scaling of semiconductor devices nears its limits, utilizing the back-side space of silicon has emerged as a new trend for future integrated circuits. With intense interest,…