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cs.CR2026
HOMARD: Hammering Off-chip Memory via Aggregate power Rail Disclosure
Eliott Quéré, Li-Chung Chiang, Carina Fiedler +6
Software-based microarchitectural attacks have mainly exploited timing differences to infer information from DRAM. However, defenses and optimizations can prevent timing-based appr…
cs.CR2026
JENGA: Exploiting Counter-Based RowHammer Countermeasures to Break Real-Time Predictability
Valentin Abgrall, Marcello Traiola, Ruben Salvador +3
Safety-critical real-time systems must satisfy multiple dependability requirements, notably time predictability and security. In such systems, tasks must complete within bounded an…