4 papers
Bit-Precise CHC Satisfiability Using Theory-Modular Reasoning
Omer Rappoport, Orna Grumberg, Yakir Vizel
Deciding satisfiability of Constrained Horn Clauses (CHCs) modulo the theory of fixed-size bit-vectors () is fundamental to bit-precise program verification. However…
Large Lemma Miners: Can LLMs do Induction Proofs for Hardware?
Romy Peled, Daniel Kroening, Michael Tautschnig +1
Large Language Models (LLMs) have shown potential for solving mathematical tasks. We show that LLMs can be utilized to generate proofs by induction for hardware verification and th…
Property Directed Reachability with Extended Resolution
Andrew Luka, Yakir Vizel
Property Directed Reachability (\textsc{Pdr}), also known as IC3, is a state-of-the-art model checking algorithm widely used for verifying safety properties. While \textsc{Pdr} is…
Revisiting DRUP-based Interpolants with CaDiCaL 2.0
Basel Khouri, Yakir Vizel
We present our implementation of DRUP-based interpolants in CaDiCaL 2.0, and evaluate performance in the bit-level model checker Avy using the Hardware Model Checking Competition b…