8 papers
Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
Ruimin Shi, Maya Gokhale, Pei-Hung Lin +2
The RISC-V Vector Extension~(RVV) is a cornerstone for supporting compute throughout in scientific and machine learning workloads. Yet compiler support and performance monitoring o…
Communication Offloading on SmartNIC DPUs: A Quantitative Approach
Jacob Wahlgren, Andong Hu, Roger Pearce +2
SmartNIC Data Processing Units (DPUs) offer a promising solution for saving high-end CPU resources by offloading tasks to programmable cores near the network interface. In this wor…
High-performance Vector-length Agnostic Quantum Circuit Simulations on ARM Processors
Ruimin Shi, Gabin Schieffer, Pei-Hung Lin +3
ARM SVE and RISC-V RVV are emerging vector architectures in high-end processors that support vectorization of flexible vector length. In this work, we leverage an important workloa…
Dissecting CPU-GPU Unified Physical Memory on AMD MI300A APUs
Jacob Wahlgren, Gabin Schieffer, Ruimin Shi +4
Discrete GPUs are a cornerstone of HPC and data center systems, requiring management of separate CPU and GPU memory spaces. Unified Virtual Memory (UVM) has been proposed to ease t…
Inter-APU Communication on AMD MI300A Systems via Infinity Fabric: a Deep Dive
Gabin Schieffer, Jacob Wahlgren, Ruimin Shi +4
The ever-increasing compute performance of GPU accelerators drives up the need for efficient data movements within HPC applications to sustain performance. Proposed as a solution t…
ARM SVE Unleashed: Performance and Insights Across HPC Applications on Nvidia Grace
Ruimin Shi, Gabin Schieffer, Maya Gokhale +3
Vector architectures are essential for boosting computing throughput. ARM provides SVE as the next-generation length-agnostic vector extension beyond traditional fixed-length SIMD.…