34 citations · 55 across the 12 of their papers we have counts for
3 papers · 1 filter
A Phase Lookahead DTC for Fast Settling Switched Loop DPLL
Pallavi Paliwal, Vivek Yadav, Shalabh Gupta
In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency t…
Trade-off between Settling Time and Jitter in Phase Locked Loop
Pallavi Paliwal, Mohanrao Sattineni, Shalabh Gupta
Most PLL architectures have inherent trade-off between settling time and jitter. This trade-off is ignored by commonly used Figure of Merit (FoM) for PLL, which considers only jitt…
Power Scaling in High Speed Analog-to-Digital Converters using Photonic Time Stretch Technique
Shalabh Gupta, George C. Valley, Robert H. Walden +1
Factors that contribute to the rapid increase in power dissipation as a function of input bandwidth in high speed electronic Analog-to-Digital Converters (ADCs) are discussed. We f…