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physics.ins-det2012
Trade-off between Settling Time and Jitter in Phase Locked Loop
Pallavi Paliwal, Mohanrao Sattineni, Shalabh Gupta
Most PLL architectures have inherent trade-off between settling time and jitter. This trade-off is ignored by commonly used Figure of Merit (FoM) for PLL, which considers only jitt…
physics.ins-det2009★ 2 cited
Power Scaling in High Speed Analog-to-Digital Converters using Photonic Time Stretch Technique
Shalabh Gupta, George C. Valley, Robert H. Walden +1
Factors that contribute to the rapid increase in power dissipation as a function of input bandwidth in high speed electronic Analog-to-Digital Converters (ADCs) are discussed. We f…