4 papers · 1 filter
ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
Runkai Li, Jia Xiong, Xiuyuan He +5
High-Level Synthesis (HLS) improves IC development productivity by enabling hardware design from C-like languages. However, strict coding constraints and design-specific optimizati…
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
Lik Tung Fu, Jie Zhou, Shaokai Ren +6
Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced sim…
FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification
Gwok-Waa Wan, Shengchu Su, Ruihu Wang +15
Despite the transformative potential of Large Language Models (LLMs) in hardware design, a comprehensive evaluation of their capabilities in design verification remains underexplor…
iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs
Runkai Li, Jia Xiong, Xi Wang
High-Level Synthesis (HLS) serves as an agile hardware development tool that streamlines the circuit design by abstracting the register transfer level into behavioral descriptions,…