5 papers
MicroEvo: Knowledge-Guided LLM Sampling for Efficient Microarchitecture Design Space Exploration
Jia Xiong, Runkai Li, Chenxu Niu +11
Microarchitecture design space exploration suffers from expansive search spaces and expensive PPA evaluation, leaving only a small simulation budget for design decision-making. Exi…
ZK-Tracer: A High-Performance Heterogeneous Accelerator for Zero-Knowledge VM Trace Generation
Jieran Cui, Zhengkai Wen, Haowen Fang +6
Zero-knowledge virtual machines (zkVMs) are a key technology for driving the large-scale adoption of zero-knowledge proofs (ZKP), but their performance bottlenecks severely limit t…
ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
Runkai Li, Jia Xiong, Xiuyuan He +5
High-Level Synthesis (HLS) improves IC development productivity by enabling hardware design from C-like languages. However, strict coding constraints and design-specific optimizati…
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
Lik Tung Fu, Jie Zhou, Shaokai Ren +6
Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced sim…
iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs
Runkai Li, Jia Xiong, Xi Wang
High-Level Synthesis (HLS) serves as an agile hardware development tool that streamlines the circuit design by abstracting the register transfer level into behavioral descriptions,…