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cs.AR2026
VeriPilot: An LLM-Powered Verilog Debugging Framework
Yihan Wang, Cheng Liu, Jiazheng Zhang +4
Verilog debugging remains one of the most time-consuming stages in digital circuit design. Recent advances in Large Language Models (LLMs) have enabled automated debugging; however…
cs.AR2024★ 1 cited
IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA
Zesong Jiang, Qing Zhang, Cheng Liu +3
Open-source EDA tools are rapidly advancing, fostering collaboration, innovation, and knowledge sharing within the EDA community. However, the growing complexity of these tools, ch…