2 papers
cs.CL2026
Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation
Zehua Pei, Hui-Ling Zhen, Yu Zhang +3
Large language models (LLMs) have improved Verilog generation from natural-language specifications, but most pipelines still treat generation as isolated sampling followed by funct…
cs.LG2025
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
Reza Moravej, Saurabh Bodhe, Zhanguang Zhang +6
Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditi…