most citedDesigning Efficient LLM Accelerators for Edge Devices

4 citations · 4 across the 4 of their papers we have counts for

collaborators

5 papers

cs.AR2026

FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining

Rappy Saha, Nima Amirafshar, Jude Haris +2

Approximate multipliers can reduce hardware area and energy consumption in Deep Neural Network (DNN) inference; however, they introduce computational errors. Assessing the accuracy…

cs.AR2026

FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers

Hubert Dymarkowski, Xingjian Fu, Rappy Saha +2

Deploying Vision Transformer (ViT) models on edge platforms remains challenging due to their high computational demands and the architectural heterogeneity of modern hybrid ViT mod…

cs.AR2026

PoTAcc: A Pipeline for End-to-End Acceleration of Power-of-Two Quantized DNNs

Rappy Saha, Jude Haris, Nicolas Bohm Agostini +2

Power-of-two (PoT) quantization significantly reduces the size of deep neural networks (DNNs) and replaces multiplications with bit-shift operations for inference. Prior work has s…

cs.AR2024

Accelerating PoT Quantization on Edge Devices

Rappy Saha, Jude Haris, José Cano

Non-uniform quantization, such as power-of-two (PoT) quantization, matches data distributions better than uniform quantization, which reduces the quantization error of Deep Neural…

cs.AR2024★ 4 cited

Designing Efficient LLM Accelerators for Edge Devices

Jude Haris, Rappy Saha, Wenhao Hu +1

The increase in open-source availability of Large Language Models (LLMs) has enabled users to deploy them on more and more resource-constrained edge devices to reduce reliance on n…