2 papers
cs.AR2024
Verifying Non-friendly Formal Verification Designs: Can We Start Earlier?
Bryan Olmos, Daniel Gerl, Aman Kumar +1
The design of Systems on Chips (SoCs) is becoming more and more complex due to technological advancements. Missed bugs can cause drastic failures in safety-critical environments le…
cs.SE2024
The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages
Johannes Schreiner, Daniel Gerl, Robert Kunzelmann +2
The rapid evolution of Integrated Circuit (IC) development necessitates innovative methodologies such as code generation to manage complexity and increase productivity. Using the r…