3 citations · 3 across the 4 of their papers we have counts for
5 papers
Climbing the Design Ladder: Sequential Knowledge Distillation for Early-Stage Circuit Timing Prediction
Reza Moravej, Fahad Rahman Amik, Zhanguang Zhang +2
Integrated circuit design involves multiple design stages: logic synthesis, floorplanning, placement, and routing, with each stage taking hours to weeks to complete. Discovering ti…
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
Reza Moravej, Saurabh Bodhe, Zhanguang Zhang +6
Logic synthesis is a crucial phase in the circuit design process, responsible for transforming hardware description language (HDL) designs into optimized netlists. However, traditi…
Scalable Graph Self-Supervised Learning
Ali Saheb Pasand, Reza Moravej, Mahdi Biparva +2
In regularization Self-Supervised Learning (SSL) methods for graphs, computational complexity increases with the number of nodes in graphs and embedding dimensions. To mitigate the…
WERank: Towards Rank Degradation Prevention for Self-Supervised Learning Using Weight Regularization
Ali Saheb Pasand, Reza Moravej, Mahdi Biparva +1
A common phenomena confining the representation quality in Self-Supervised Learning (SSL) is dimensional collapse (also known as rank degeneration), where the learned representatio…
Deep Policies for Online Bipartite Matching: A Reinforcement Learning Approach
Mohammad Ali Alomrani, Reza Moravej, Elias B. Khalil
The challenge in the widely applicable online matching problem lies in making irrevocable assignments while there is uncertainty about future inputs. Most theoretically-grounded po…