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Jeries Mattar

2 papers hereh-index 00 citations1 works total

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author position
  • first author2

Across the 2 of 2 papers where every author was matched, so the position is known.

fields
  • cs.ET2

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collaborators

2 papers

cs.ET2026

A FeFET Voltage-to-Time Converter with Offset Trim by Programmed Multilevel State in 28-nm CMOS

Jeries Mattar, Hanaa Eqeiq, Stefan Dünkel +4

The offset and gain of voltage-to-time converters (VTCs) in time-domain circuits vary with process, supply, and temperature. This work presents a VTC whose nonvolatile input-referr…

cs.ET2025

A Reconfigurable Time-Domain In-Memory Computing Macro using FeFET-Based CAM with Multilevel Delay Calibration in 28 nm CMOS

Jeries Mattar, Mor M. Dahan, Stefan Dunkel +5

Time-domain nonvolatile in-memory computing (TD-nvIMC) offers a promising pathway to reduce data movement and improve energy efficiency by encoding computation in delay rather than…

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