2 papers
cs.CL2026
OpenRTLSet: A Fully Open-Source Dataset for Large Language Model-based Verilog Module Design
Jinghua Wang, Lily Jiaxin Wan, Sanjana Pingali +6
OpenRTLSet introduces the largest fully open-source dataset for hardware design, offering over 131,000 diverse Verilog code samples to the research community and industry. Our data…
cs.LG2025
QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
Yaoyu Zhu, Di Huang, Hanqi Lyu +16
Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification, such as…