3 papers
cs.AR2026
FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling
Roberto Giorgi, Miquel Moretó Planas
FREESS (Free Educational Superscalar Simulator) is an open-source teaching environment for instruction-level parallelism in a RISC-V-inspired superscalar processor. It provides a c…
cs.AR2025
FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm
Roberto Giorgi
FREESS is a free, interactive simulator that illustrates instruction-level parallelism in a RISC-V-inspired superscalar processor. Based on an extended version of Tomasulo's algori…
cs.AR2025
WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
Roberto Giorgi, Gianfranco Mariotti
WebRISC-V is a web-based educational tool designed to simulate the pipelined execution of assembly programs according to the RV64IM specifications (64-bit RISC-V processor). The to…