6 papers
Partitioning-free 3D-IC Floorplanning
Shuo Ren, Rongliang Fu, Libo Shen +5
3D integration with fine-pitch hybrid bonding offers a promising path to alleviate interconnect bottlenecks in conventional two-dimensional (2D) ICs, yet efficient 3D floorplanning…
CSCO: A Backside-PDN-Aware Clock-Signal Co-Optimization Framework for Improved PPA
Zixiao Wang, Leilei Jin, Zhen Zhuang +2
Backside power delivery networks (BSPDN) have emerged as a promising technology for advanced logic nodes to address IR-drop and PPA challenges. While BSPDN introduces additional ro…
CLIP-3D: Closed-Loop Evaluation of Performance and Physical Constraints for 3D ICs
Shuo Ren, Libo Shen, Yaohui Han +6
3D integration packs more power into a smaller footprint, so a candidate design's actual throughput depends on its layout: which macro sits on which tier, where the hot spot lands,…
AgenticPD: A Stage-Aware Agentic Framework for Closed-Loop Physical Design Optimization
Shuo Ren, Zijin Cheng, Yaohui Han +7
Physical design quality-of-results (QoR) optimization is hard and expensive. Choices made at one stage can help or hurt later stages. Each evaluation requires a costly EDA run thro…
R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII
Zewei Zhou, Jiajun Zou, Jiajia Zhang +8
Graph neural networks (GNNs) are increasingly applied to physical design tasks such as congestion prediction and wirelength estimation, yet progress is hindered by inconsistent cir…
A Crosstalk-Aware Timing Prediction Method in Routing
Leilei Jin, Jiajie Xu, Wenjie Fu +2
With shrinking interconnect spacing in advanced technology nodes, existing timing predictions become less precise due to the challenging quantification of crosstalk-induced delay.…