1 citations · 1 across the 1 of their papers we have counts for
2 papers
cs.AR2026
SVRF: Efficient Register Storage for Long-Vector Architectures
Francesco Minervini, Lorenzo Deltetto, Osman Unsal +1
Vector processors exploit data-level parallelism to provide high computational throughput, but very long vectors can make the Vector Register File (VRF) a significant source of are…
cs.AR2026★ 1 cited
EPAC: The Last Dance
Filippo Mantovani, Fabio Banchelli, Pablo Vizcaino +36
This paper presents EPAC, a RISC-V-based accelerator chip developed within the European Processor Initiative (EPI) as part of a multi-year, multi-partner effort to build a European…