4 papers
Process-Technology Co-optimization for 2D-FETs
Shao-Heng Yang, Jainil Dharmil Shah, Mayukh Das +15
We present the first experimental machine learning (ML)-enabled Process-Technology Co-Optimization (PTCO) framework for optimizing 2D transition metal dichalcogenide (TMD) FET fabr…
Spin Vector Control for Heisenberg-Inspired Probabilistic Computing
Yuanqiu Tan, Rahul Tripathi, Saleh Bunaiyan +5
Probabilistic bits (p-bits) have emerged as a cornerstone of probabilistic computing, enabling energy-efficient hardware implementation for probabilistic inference and combinatoria…
Experimental Demonstration of an On-Chip CMOS-Integrated 3T-1MTJ Probabilistic Bit -- A P-Bit
Xuejian Zhang, John Arnesh Divakaruni Daniel, Neil Dilley +2
Ongoing semiconductor scaling challenges and the rise of neuromorphic computing have sparked interest in exploring novel computing schemes to achieve higher power efficiency and co…
Scaling Two-Dimensional Semiconductor Nanoribbons for High-Performance Electronics
Hao-Yu Lan, Shao-Heng Yang, Yongjae Cho +10
As silicon transistors scale toward future technology nodes, three-dimensional architectures -- including gate-all-around (GAA) nanoribbon and complementary field-effect transistor…