7 citations · 7 across the 2 of their papers we have counts for
2 papers
cs.AR2026
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Sajjad Ahmed, Alexander Kropotov, Roberto Ignacio Genovese +21
The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, w…
cs.AR2024★ 7 cited
Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs
Elias Perdomo, Alexander Kropotov, Francelly Cano +4
Emulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidates for such purpos…