2 papers
cs.AR2026
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
Sajjad Ahmed, Alexander Kropotov, Roberto Ignacio Genovese +21
The Barcelona Zetascale Lab (BZL) project aims to strengthening Europe's capacity in the design and manufacture of RISC-V based high-performance computing chips. In this context, w…
cs.AR2023
PPU: Design and Implementation of a Pipelined Full Posit Processing Unit
Federico Rossi, Francesco Urbani, Marco Cococcioni +2
By exploiting the modular RISC-V ISA this paper presents the customization of instruction set with posit\textsuperscript{\texttrademark} arithmetic instructions to provide improved…