4 papers
GoGoTB: Agentic RTL Verification with Specification-Grounded Coverage Closure
Xin Xin, Jincheng Lou, Junhui Li +11
Functional verification dominates integrated circuit (IC) front-end engineering effort, and a single missed bug that escapes to silicon can trigger a costly respin. Recent large la…
PANDA: An LLM-Enhanced Performance-Driven Analog Design Framework Bridging Design Intent and Layout Generation
Haoyi Zhang, Weijian Fan, Xiaohan Gao +3
Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation. In this work…
DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams
Jincheng Lou, Ruohan Xu, Jiapeng Li +6
System-level diagrams encode the architectural blueprint of chip design, specifying module functions, dataflows, and interface protocols. However, non-standardized symbols and the…
KATO: Knowledge Alignment and Transfer for Transistor Sizing of Different Design and Technology
Wei W. Xing, Weijian Fan, Zhuohua Liu +2
Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specif…