4 papers
Wire-Level Interrupt-to-Decision Latency of On-Sensor MLC versus Host Inference on the NVIDIA Jetson Orin Nano: A Pre-Registered Measurement Study
Akul Swami, Dnyaneshwar Sonawane
The Machine Learning Core (MLC) embedded in the STMicroelectronics LSM6DSOX IMU is widely cited as a low-latency alternative to host-side inference, yet wire-level decision-deliver…
Architecture Dependent Temporal Observability Under Deployment Interference in Edge Inference Systems
Akul Swami, Nikhil Chougule
Edge inference systems are typically evaluated with software-reported latency collected under controlled conditions. We argue, and demonstrate empirically, that deployment interfer…
Per-Platform GPIO Overhead in Hardware-Validated Edge ML Inference Timing
Akul Swami, Nikhil Chougule
Edge machine learning (ML) deployments increasingly rely on per-inference timing measured by software clocks such as Python's perf_counter, but these measurements are not always va…
Architectural Isolation as a Timing Safety Primitive for Edge AI Medical Devices: Controlled Experimental Evidence on a Shared-Silicon Platform
Akul Mallayya Swami
A system can satisfy accuracy-based validation, maintain output stability (Safety-Threshold Exceedance Rate, STER, equal to zero), and still violate timing constraints under deploy…