8 papers
Assessing Triple Modular Redundancy for Wide-Link, Low-Latency NoC Routers: Reliability and Physical Design Challenges
Chen Wu, Michael Rogenmoser, Luca Benini +1
Protecting the Network-on-Chip (NoC) of physical-AI tile-based accelerators deployed in harsh environments against single-event effects (SEEs) is paramount for preventing NoC failu…
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
Lorenzo Leone, Philip Wiese, Gamze Ä°slamoÄlu +4
We present Chimera, a flexible and scalable Microcontroller Unit (MCU) designed to accelerate real-time inference of rapidly evolving transformer-based models at the ultra-low-powe…
Who Checks the Checker? Enhancing Component-level Architectural SEU Fault Tolerance for End-to-End SoC Protection
Michael Rogenmoser, Philippe Sauter, Chen Wu +2
Single-event upset (SEU) fault tolerance for systems-on-chip (SoCs) in radiation-heavy environments is often addressed by architectural fault-tolerance approaches protecting indivi…
A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
Thomas Benz, Axel Vanoni, Michael Rogenmoser +1
With the ever-growing heterogeneity in computing systems, driven by modern machine learning applications, pressure is increasing on memory systems to handle arbitrary and more dema…
relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
Michael Rogenmoser, Angelo Garofalo, Luca Benini
On-chip communication is a critical element of modern systems-on-chip (SoCs), allowing processor cores to interact with memory and peripherals. Interconnects require special care i…
Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
Michael Rogenmoser, Philip Wiese, Bruno Endres Forlin +5
RISC-V-based fault-tolerant system-on-chip (SoC) designs are critical for the new generation of automotive and space SoC architectures. However, reliability assessment requires cha…