3 papers
cs.AR2026
EstRTL: Functional Estimation Guided RTL Code Generation
Qi Xiong, Renzhi Chen, Bowei Wang +3
Optimizing register transfer level (RTL) code is of vital importance in hardware design. Large language models (LLMs) provide new methods for the automatic generation and optimizat…
cs.AI2025
ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development
Bowei Wang, Jiaran Gao, Yelai Feng +3
The growing demand for Domain-Specific Architecture (DSA) has driven the development of Agile Hardware Development Methodology (AHDM). Hardware Construction Language (HCL) like Chi…
cs.AR2025
RTLSquad: Multi-Agent Based Interpretable RTL Design
Bowei Wang, Qi Xiong, Zeqing Xiang +2
Optimizing Register-Transfer Level (RTL) code is crucial for improving hardware PPA performance. Large Language Models (LLMs) offer new approaches for automatic RTL code generation…