5 papers
EstRTL: Functional Estimation Guided RTL Code Generation
Qi Xiong, Renzhi Chen, Bowei Wang +3
Optimizing register transfer level (RTL) code is of vital importance in hardware design. Large language models (LLMs) provide new methods for the automatic generation and optimizat…
IncreRTL: Traceability-Guided Incremental RTL Generation under Requirement Evolution
Luanrong Chen, Renzhi Chen, Xinyu Li +3
Large language models (LLMs) have shown promise in generating RTL code from natural-language descriptions, but existing methods remain static and struggle to adapt to evolving desi…
ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile Hardware Development
Bowei Wang, Jiaran Gao, Yelai Feng +3
The growing demand for Domain-Specific Architecture (DSA) has driven the development of Agile Hardware Development Methodology (AHDM). Hardware Construction Language (HCL) like Chi…
LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
Zhigang Fang, Renzhi Chen, Zhijie Yang +3
Code Linting tools are vital for detecting potential defects in Verilog code. However, the limitations of traditional Linting tools are evident in frequent false positives and redu…
RTLSquad: Multi-Agent Based Interpretable RTL Design
Bowei Wang, Qi Xiong, Zeqing Xiang +2
Optimizing Register-Transfer Level (RTL) code is crucial for improving hardware PPA performance. Large Language Models (LLMs) offer new approaches for automatic RTL code generation…