3 papers
cs.AR2026
VeriBugBench: An Empirically Grounded Framework for Constructing Verilog RTL Debugging Benchmarks
Xiankai Meng, Kejian Feng, Xinlin Zhao +4
RTL source-level debugging research requires benchmark artifacts that provide faulty designs together with precise change locations, executable test stimuli, and reproducible confi…
cs.SE2026
Debug Like a Human: Scaling LLM-based Fault Localization to Processor Design via Block-Level Instruction-Oriented Slicing
Zizhen Liu, Xiaoguang Mao, Deheng Yang +6
Fault localization in modern processor design code is a critical yet time-consuming step during processor verification. While recent advances in LLM-based techniques for module-lev…
cs.SE2024
Fault Localization from the Semantic Code Search Perspective
Yihao Qin, Shangwen Wang, Yan Lei +5
The software development process is characterized by an iterative cycle of continuous functionality implementation and debugging, essential for the enhancement of software quality…