50 citations · 55 across the 4 of their papers we have counts for
4 papers
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
Gabriel Torrens, Bartomeu Alorda, Cristian Carmona +3
As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values compr…
Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment
Daniel Malagon, Gabriel Torrens, Jaume Segura +1
We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistors (6T) and eight-transistors (8T) bit-cells S…
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs
J. L. Rossello, V. Canals, S. A. Bota +2
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperatu…
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs
S. A. Bota, M. Rosales, J. L. Rossello +1
In this paper we present a simple and efficient built-in temperature sensor for thermal monitoring of standard-cell based VLSI circuits. The proposed smart temperature sensor uses…