72 citations · 78 across the 3 of their papers we have counts for
3 papers
cs.CV2026
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
Chia-Tung Ho, Haoyu Yang, Guanglei Zhou +6
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, d…
cs.AR2024★ 6 cited
DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
Chen-Chia Chang, Chia-Tung Ho, Yaguang Li +2
In the advanced technology nodes, the integrated design rule checker (DRC) is often utilized in place and route tools for fast optimization loops for power-performance-area. Implem…
cs.AR2020★ 72 cited
ALIGN: A System for Automating Analog Layout
Tonmoy Dhar, Kishor Kunal, Yaguang Li +11
ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an…