Compact Modeling of 0.35 micron SOI CMOS Technology Node for 4 K DC Operation using Verilog-A

A. Akturk, K. Eng, J. Hamlet +7

Compact modeling of MOSFETs from a 0.35 micron SOI technology node operating at 4 K is presented. The Verilog-A language is used to modify device equations for BSIM models and more…