activity
20222026
most citedA Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS

6 citations · 25 across the 9 of their papers we have counts for

collaborators

9 papers

cs.AI2026

JEV-as-a-Judge: Accept When Confident, Escalate When Unsure

Yubo Li, Yidi Miao, Ramayya Krishnan +1

LLM-as-a-judge scales evaluation, but reasoning judges are slow and costly. We study JEV-as-a-Judge: evaluation with JEV, a decision-only judge that returns label probabilities ins…

cs.AR2025★ 1 cited

Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems

Davide Zoni, Andrea Galimberti, Adriano Guarisco

Designing and validating efficient cache-coherent memory subsystems is a critical yet complex task in the development of modern multi-core system-on-chip architectures. Rhea is a u…

cs.AR2025★ 4 cited

A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs

Andrea Galimberti, Gabriele Montanaro, Andrea Motta +2

FPGAs are increasingly utilized in data centers due to their capacity to exploit data parallelism in computationally intensive workloads. Furthermore, the processing of modern data…

cs.AR2024★ 6 cited

A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS

Gabriele Montanaro, Andrea Galimberti, Davide Zoni

Frameworks for the agile development of modern system-on-chips are crucial to dealing with the complexity of designing such architectures. The open-source Vespa framework for desig…

cs.AR2024★ 1 cited

Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms

Andrea Galimberti, Michele Piccoli, Davide Zoni

The current over-provisioned heterogeneous multi-cores require effective run-time optimization strategies, and the run-time power monitoring subsystem is paramount for their succes…

cs.AR2024★ 1 cited

Functional ISS-Driven Verification of Superscalar RISC-V Processors

Andrea Galimberti, Marco Vitali, Sebastiano Vittoria +1

A time-efficient and comprehensive verification is a fundamental part of the design process for modern computing platforms, and it becomes ever more important and critical to optim…

cs.CR2024★ 6 cited

An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research

Davide Zoni, Andrea Galimberti, Davide Galli

Attacks based on side-channel analysis (SCA) pose a severe security threat to modern computing platforms, further exacerbated on IoT devices by their pervasiveness and handling of…

cs.CR2022

An Evaluation of the State-of-the-Art Software and Hardware Implementations of BIKE

Andrea Galimberti, Gabriele Montanaro, William Fornaciari +1

NIST is conducting a process for the standardization of post-quantum cryptosystems, i.e., cryptosystems that are resistant to attacks by both traditional and quantum computers and…

cs.AR2022★ 6 cited

Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators

Gabriele Montanaro, Andrea Galimberti, Ernesto Colizzi +1

In order to mitigate the security threat of quantum computers, NIST is undertaking a process to standardize post-quantum cryptosystems, aiming to assess their security and speed up…