15 citations · 17 across the 3 of their papers we have counts for
5 papers
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing
Mattia Sinigaglia, Amirhossein Kiamarzi, Marco Bertuletti +11
Most Wearable Ultrasound (WUS) devices lack the computational power to process signals at the edge, instead relying on remote offload, which introduces latency, high power consumpt…
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti +20
Next-generation mixed-criticality Systems-on-chip (SoCs) for robotics, automotive, and space must execute mixed-criticality AI-enhanced sensor processing and control workloads, ens…
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
Matteo Perotti, Michele Raeber, Mattia Sinigaglia +3
Multi-core vector processor architectures excel in handling computationally intensive vectorizable tasks but struggle to achieve optimal resource utilization when facing sequential…
A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems
Chaoqun Liang, Alessandro Ottaviano, Thomas Benz +4
The ongoing revolution in application domains targeting autonomous navigation, first and foremost automotive "zonalization", has increased the importance of certain off-chip commun…
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
Luca Valente, Alessandro Nadalini, Asif Veeran +12
The rapid advancement of energy-efficient parallel ultra-low-power (ULP) ucontrollers units (MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles (na…