1 citations · 1 across the 2 of their papers we have counts for
2 papers
cs.AR2025★ 1 cited
VFlow: Discovering Optimal Agentic Workflows for Verilog Generation
Yangbo Wei, Zhen Huang, Huang Li +3
Hardware design automation faces challenges in generating high-quality Verilog code efficiently. This paper introduces VFlow, an automated framework that optimizes agentic workflow…
cs.LG2024
KATO: Knowledge Alignment and Transfer for Transistor Sizing of Different Design and Technology
Wei W. Xing, Weijian Fan, Zhuohua Liu +2
Automatic transistor sizing in circuit design continues to be a formidable challenge. Despite that Bayesian optimization (BO) has achieved significant success, it is circuit-specif…