33 citations · 58 across the 16 of their papers we have counts for
11 papers · 1 filter
YAVIN: A Unified Architecture for Secure Edge Processing in Memory
Shouzhi Fang, William C. Tegge, Md Omar Faruque +3
Secure, private multi-tenant execution spanning processors, memory, and accelerators remains one of the most significant challenges in modern edge computing systems. Simultaneously…
μ-ORCA: Optimizing Acceleration for Microsecond-Scale Deep Neural Network Inference on ACAP
Shixin Ji, Jinming Zhuang, Zhuoping Yang +3
Heterogeneous reconfigurable platforms with tensor cores, such as AMD ACAP, are increasingly adopted for deep neural network (DNN) inference due to their high throughput and flexib…
DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration
Xingzhen Chen, Zhuoping Yang, Jinming Zhuang +5
As deep neural networks develop significantly more diverse and complex, achieving high performance and efficiency on complicated DNN models faces pressing challenges. Modern DNN wo…
To Overlay or to Customize? Revisiting Architectural Choices in Heterogeneous Systems
Xingzhen Chen, Shixin Ji, Zheng Dong +1
In this work, we present a systematic study of this trade-off from a deployment-centric perspective, focusing on an autonomous driving scenario. Instead of treating overlay and cus…
FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration
Xingzhen Chen, Jinming Zhuang, Zhuoping Yang +5
With the development of deep neural network (DNN) enabled applications, achieving high hardware resource efficiency on diverse workloads is non-trivial in heterogeneous computing p…
PHAROS: Pipelined Heterogeneous Accelerators for Real-time Safety-critical Systems With Deadline Compliance
Shixin Ji, Jinming Zhuang, Sarah Schultz +6
Spatially partitioned heterogeneous accelerators (HAs) are increasingly adopted in embedded systems for their performance and flexibility. Yet most existing HA design frameworks op…
Towards Error Correction for Computing in Racetrack Memory
Preston Brazzle, Benjamin F. Morris, Evan McKinney +4
Computing-in-memory (CIM) promises to alleviate the Von Neumann bottleneck and accelerate data-intensive applications. Depending on the underlying technology and configuration, CIM…
SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration
Jinming Zhuang, Zhuoping Yang, Shixin Ji +5
With the increase in the computation intensity of the chip, the mismatch between computation layer shapes and the available computation resource significantly limits the utilizatio…
REFRESH FPGAs: Sustainable FPGA Chiplet Architectures
Peipei Zhou, Jinming Zhuang, Stephen Cahoon +6
There is a growing call for greater amounts of increasingly agile computational power for edge and cloud infrastructure to serve the computationally complex needs of ubiquitous com…
Challenges and Opportunities to Enable Large-Scale Computing via Heterogeneous Chiplets
Zhuoping Yang, Shixin Ji, Xingzhen Chen +4
Fast-evolving artificial intelligence (AI) algorithms such as large language models have been driving the ever-increasing computing demands in today's data centers. Heterogeneous c…
AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP
Zhuoping Yang, Jinming Zhuang, Jiaqi Yin +3
Arbitrary-precision integer multiplication is the core kernel of many applications in simulation, cryptography, etc. Existing acceleration of arbitrary-precision integer multiplica…