9 citations · 14 across the 9 of their papers we have counts for
10 papers
Exposing Embedded Matrix Multiplication with polyhedral transformations for CGRA compilation
Yuxuan Wang, María José Belda, Fernando Castro +3
Matrix-matrix multiplication (mmul) is a dominant computing pattern in edge workloads, but in real applications it is often embedded within larger affine programs and intertwined w…
Mitigating the Bandwidth Wall via Data-Streaming System-Accelerator Co-Design
Qunyou Liu, Marina Zapater, David Atienza
Transformers have revolutionized AI in natural language processing and computer vision, but their large computation and memory demands pose major challenges for hardware accelerati…
An MLIR-Based Compilation Framework for Control Flow Management on Coarse Grained Reconfigurable Arrays
Yuxuan Wang, Cristian Tirelli, Giovanni Ansaloni +2
Coarse Grained Reconfigurable Arrays (CGRAs) present both high flexibility and efficiency, making them well-suited for the acceleration of intensive workloads. Nevertheless, a key…
A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
Maxime Henri Aspros, Juan Sapriza, Giovanni Ansaloni +1
At the intersection between traditional CPU architectures and more specialized options such as FPGAs or ASICs lies the family of reconfigurable hardware architectures, termed Coars…
MatrixFlow: System-Accelerator co-design for high-performance transformer applications
Qunyou Liu, Marina Zapater, David Atienza
Transformers are central to advances in artificial intelligence (AI), excelling in fields ranging from computer vision to natural language processing. Despite their success, their…
Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators
Qunyou Liu, Marina Zapater, David Atienza
The growing demand for efficient, high-performance processing in machine learning (ML) and image processing has made hardware accelerators, such as GPUs and Data Streaming Accelera…
Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
Pedro Palacios, Rafael Medina, Jean-Luc Rouas +2
Efficient deployment of resource-intensive transformers on edge devices necessitates cross-stack optimization. We thus study the interrelation between structured pruning and systol…
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs
Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez +6
Coarse-Grain Reconfigurable Arrays (CGRAs) represent emerging low-power architectures designed to accelerate Compute-Intensive Loops (CILs). The effectiveness of CGRAs in providing…
LionHeart: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles
Corey Lammie, Yuxuan Wang, Flavio Ponzina +7
When arranged in a crossbar configuration, resistive memory devices can be used to execute Matrix-Vector Multiplications (MVMs), the most dominant operation of many Machine Learnin…
Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures
Alireza Amirshahi, Giovanni Ansaloni, David Atienza
The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles th…