4 papers
Exploiting the Uncertainty of the Longest Paths: Response Time Analysis for Probabilistic DAG Tasks
Yiyang Gao, Shuai Zhao, Boyang Li +4
Parallel real-time systems (e.g., autonomous driving systems) often contain functionalities with complex dependencies and execution uncertainties, leading to significant timing var…
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
Junhao Ye, Yuchen Hu, Ke Xu +8
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of the total development effort. While the Universal Verification Methodology…
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
Jie Zhou, Youshu Ji, Ning Wang +7
SystemVerilog Assertions (SVAs) are essential for verifying Register Transfer Level (RTL) designs, as they can be embedded into key functional paths to detect unintended behaviours…
Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors
Renshuang Jiang, Pan Dong, Zhenling Duan +6
To provide flexibility and low-level interaction capabilities, the unsafe tag in Rust is essential in many projects, but undermines memory safety and introduces Undefined Behaviors…