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Monte Cimone v2: Down the Road of RISC-V High-Performance Computers
Emanuele Venieri, Simone Manoni, Gabriele Ceccolini +6
Many RISC-V (RV) platforms and SoCs have been announced in recent years targeting the HPC sector, but only a few of them are commercially available and engineered to fit the HPC re…
SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
Simone Manoni, Paul Scheffler, Luca Zanatta +3
Spiking Neural Network (SNN) inference has a clear potential for high energy efficiency as computation is triggered by events. However, the inherent sparsity of events poses challe…
Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6
Umberto Laghi, Simone Manoni, Emanuele Parisi +1
In this work, we present the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. We integrat…