95 citations · 108 across the 8 of their papers we have counts for
Showing 2024Show all
3 papers · 1 filter
cs.AR2024
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Zhiyuan Yan, Wenji Fang, Mengming Li +4
Assertion-based verification (ABV) is a critical method to ensure logic designs comply with their architectural specifications. ABV requires assertions, which are generally convert…
cs.AR2024
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
Wenji Fang, Shang Liu, Hongce Zhang +1
In digital IC design, compared with post-synthesis netlists or layouts, the early register-transfer level (RTL) stage offers greater optimization flexibility for both designers and…
cs.AR2024★ 8 cited
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Wenji Fang, Mengming Li, Min Li +4
Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural langua…