13 papers
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1
Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering…
SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation
Mahshid Rezakhani, Nowfel Mashnoor, Kimia Azar +1
As large language models (LLMs) are increasingly fine-tuned for hardware tasks like RTL code generation, the scarcity of high-quality datasets often leads to the use of rapidly ass…
From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
Nowfel Mashnoor, Hadi Kamali, Kimia Azar
SystemVerilog Assertions (SVA) are essential for formal verification of digital hardware, yet their manual creation demands significant expertise in both the design under verificat…
Secure eFPGA-Enabled Edge LLM Inference: Architectural and Hardware Countermeasures
Voktho Das, M Zafir Sadik Khan, Jafar Vafaei +2
Edge deployment of transformer-based models increasingly relies on ASIC accelerators due to their high performance and energy efficiency, achieved through optimized dataflows, spec…
MeltRTL: Multi-Expert LLMs with Inference-time Intervention for RTL Code Generation
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
The automated generation of hardware register-transfer level (RTL) code with large language models (LLMs) shows promise, yet current solutions struggle to produce syntactically and…
Bench4HLS: End-to-End Evaluation of LLMs in High-Level Synthesis Code Generation
M Zafir Sadik Khan, Kimia Azar, Hadi Kamali
In last two years, large language models (LLMs) have shown strong capabilities in code generation, including hardware design at register-transfer level (RTL). While their use in hi…