9 papers
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
Mohammad Akyash, Nowfel Mashnoor, Kimia Azar +1
Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering…
SafeTune: Mitigating Data Poisoning in LLM Fine-Tuning for RTL Code Generation
Mahshid Rezakhani, Nowfel Mashnoor, Kimia Azar +1
As large language models (LLMs) are increasingly fine-tuned for hardware tasks like RTL code generation, the scarcity of high-quality datasets often leads to the use of rapidly ass…
From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation
Nowfel Mashnoor, Hadi Kamali, Kimia Azar
SystemVerilog Assertions (SVA) are essential for formal verification of digital hardware, yet their manual creation demands significant expertise in both the design under verificat…
MeltRTL: Multi-Expert LLMs with Inference-time Intervention for RTL Code Generation
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
The automated generation of hardware register-transfer level (RTL) code with large language models (LLMs) shows promise, yet current solutions struggle to produce syntactically and…
CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage
Nowfel Mashnoor, Mohammad Akyash, Hadi Kamali +1
Large Language Models (LLMs) have achieved remarkable success in generative tasks, including register-transfer level (RTL) hardware synthesis. However, their tendency to memorize t…
SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
M Zafir Sadik Khan, Nowfel Mashnoor, Mohammad Akyash +2
In today's rapidly evolving field of electronic design automation (EDA), the complexity of hardware designs is increasing, necessitating more sophisticated automation solutions. Hi…