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cs.LG2025
LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation
Zixi Zhang, Balint Szekely, Pedro Gimenes +5
Hardware design verification (DV) is a process that checks the functional equivalence of a hardware design against its specifications, improving hardware reliability and robustness…
cs.LG2024
Beyond Slow Signs in High-fidelity Model Extraction
Hanna Foerster, Robert Mullins, Ilia Shumailov +1
Deep neural networks, costly to train and rich in intellectual property value, are increasingly threatened by model extraction attacks that compromise their confidentiality. Previo…