4 papers
SCALE: Self-Supervised Constraint-Aware Layout GEneration for Local P&R DRV Fixing at Advanced Nodes
Chia-Tung Ho, Haoyu Yang, Guanglei Zhou +6
As semiconductor manufacturing advances toward sub-2nm nodes, local place-and-route (P&R) design-rule violation (DRV) fixing is increasingly limited by complex rule interactions, d…
Lorecast: Layout-Aware Performance and Power Forecasting from Natural Language
Runzhi Wang, Prianka Sengupta, Cristhian Roman-Vicharra +2
In chip design planning, obtaining reliable performance and power forecasts for various design options is of critical importance. Traditionally, this involves using system-level mo…
Simultaneous Multi-die Floorplanning and Technology Assignment
Cristhian Roman-Vicharra, Prianka Sengupta, Runzhi Wang +2
In heterogeneous integration, different dies may employ distinct technologies, making floorplanning across multiple dies inherently coupled with technology assignment. By assuming…
PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting
Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy +5
Generating diverse VLSI layout patterns is essential for various downstream tasks in design for manufacturing, as design rules continually evolve during the development of new tech…