3 papers
cs.DC2026
LatencyLab: A DPDK-Based P4 Pipeline Latency Measurement Framework for FPGA SmartNICs
Pavani Kuppili, Zhaoyang Han, Yicheng Qian +4
P4-programmable FPGA SmartNICs place packet processing directly on the wire, but open FPGA P4 toolflows do not expose timestamping at the pipeline boundary, so the latency a P4 pro…
cs.AR2026
Scalable Packet Tracking on FPGAs for Erasure-Coded RDMA over Lossy WANs
Yicheng Qian, Konstantin Taranov, Yevgeny Yankilevich +5
Modern AI workloads increasingly rely on scale across architectures that interconnect multiple datacenters to form a single "AI factory", overcoming the power and cooling constrain…
cs.AR2025
Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs
Zhaoyang Han, Yicheng Qian, Michael Zink +1
Sketch-based algorithms for network traffic monitoring have drawn increasing interest in recent years due to their sub-linear memory efficiency and high accuracy. As the volume of…