activity
20212025
most citedFixing Hardware Security Bugs with Large Language Models

75 citations · 158 across the 8 of their papers we have counts for

collaborators

9 papers

cs.CR2025

MARVEL: Multi-Agent RTL Vulnerability Extraction using Large Language Models

Luca Collini, Baleegh Ahmad, Joey Ah-kiow +1

Hardware security verification is a challenging and time-consuming task. Design engineers may use formal verification, linting, and functional simulation tests, coupled with analys…

cs.CR2025

LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs

Baleegh Ahmad, Hammond Pearce, Ramesh Karri +1

While static analysis is useful in detecting early-stage hardware security bugs, its efficacy is limited because it requires information to form checks and is often unable to expla…

cs.PL2023★ 10 cited

VeriGen: A Large Language Model for Verilog Code Generation

Shailja Thakur, Baleegh Ahmad, Hammond Pearce +4

In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by generating high-quality Verilog code, a common language for designing and mo…

cs.CR2023★ 3 cited

FLAG: Finding Line Anomalies (in code) with Generative AI

Baleegh Ahmad, Benjamin Tan, Ramesh Karri +1

Code contains security and functional bugs. The process of identifying and localizing them is difficult and relies on human labor. In this work, we present a novel approach (FLAG)…

cs.CR2023★ 75 cited

Fixing Hardware Security Bugs with Large Language Models

Baleegh Ahmad, Shailja Thakur, Benjamin Tan +2

Novel AI-based code-writing Large Language Models (LLMs) such as OpenAI's Codex have demonstrated capabilities in many coding-adjacent domains. In this work we consider how LLMs ma…

cs.PL2022★ 11 cited

Benchmarking Large Language Models for Automated Verilog RTL Code Generation

Shailja Thakur, Baleegh Ahmad, Zhenxing Fan +5

Automating hardware design could obviate a significant amount of human error from the engineering process and lead to fewer errors. Verilog is a popular hardware description langua…

cs.CR2022★ 22 cited

Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design

Baleegh Ahmad, Wei-Kai Liu, Luca Collini +9

To help prevent hardware security vulnerabilities from propagating to later design stages where fixes are costly, it is crucial to identify security concerns as early as possible,…

cs.CR2021★ 15 cited

Examining Zero-Shot Vulnerability Repair with Large Language Models

Hammond Pearce, Benjamin Tan, Baleegh Ahmad +2

Human developers can produce code with cybersecurity bugs. Can emerging 'smart' code completion tools help repair those bugs? In this work, we examine the use of large language mod…

cs.CR2021★ 22 cited

Asleep at the Keyboard? Assessing the Security of GitHub Copilot's Code Contributions

Hammond Pearce, Baleegh Ahmad, Benjamin Tan +2

There is burgeoning interest in designing AI-based systems to assist humans in designing computing systems, including tools that automatically generate computer code. The most nota…