2 papers
cs.PL2025
VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification
Patrick Yubeaton, Andre Nakkab, Weihua Xiao +4
This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification met…
cs.AR2024
Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
Andre Nakkab, Sai Qian Zhang, Ramesh Karri +1
Large Language Models (LLMs) are effective in computer hardware synthesis via hardware description language (HDL) generation. However, LLM-assisted approaches for HDL generation st…