7 citations · 7 across the 4 of their papers we have counts for
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cs.LO2024★ 7 cited
Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement
Hongyang Pan, Cunqing Lan, Yiting Liu +5
A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages…
cs.LO2023
A Semi-Tensor Product based Circuit Simulation for SAT-sweeping
Hongyang Pan, Ruibing Zhang, Yinshui Xia +4
In recent years, circuit simulators and Boolean satisfiability (SAT) solvers have been tightly integrated to provide efficient logic synthesis and verification. Circuit simulation…